This invention relates generally to the field of integrated circuits and particularly to such integrated circuits having at least a portion of the active circuitry positioned under the bond pads. More particularly, the invention relates to a process for forming such a bond pad.
As today""s advancing semiconductor processing technology allows for higher integration levels within integrated circuit devices, it becomes increasingly more important to fully utilize the space available within the substrates on which the integrated circuit devices are produced. An integrated circuit device is also known as a chip especially when it is still included within the semiconductor substrate on which it is formed. Chip size is determined, in large part, by the density and number of individual devices which combine to form a completed integrated circuit device. By minimizing or reducing chip size, more chips can be created within a substrate of a fixed dimension, and production costs are therefore decreased.
Each integrated circuit device includes a number of bond pads which are used to provide for electrical connection to external components. More specifically, the electrical connections between the external pins of an assembled integrated circuit package and the integrated circuit itself, are made through bond pads which are generally located on the periphery of the chip. Bond pads are metal areas which are electrically connected to the multitude of individual devices which combine to form the integrated circuit, via buffers and other electrically conducting interconnects. Due to conventional bonding technology used to couple external conductive wires to the bond pads, and also due to design constraints, the bond pads have relatively large dimensions when compared to other features such as transistors or other individual devices which combine to form the integrated circuit device. Therefore, bond pads occupy or cover a significant portion of the chip surface. The area underneath the bond pads thus occupies a substantial fraction of the surface of the substrate comprising the chip. Conventionally, the area used to form the bond pads, in a sense, came at the expense of area which could be used to form other devices of the integrated circuit. It can be therefore understood that providing active devices beneath the bond pads increases the level of integration of the integrated circuit device and may also allow for a reduced chip size.
The electrical connection between the package and the bond pad requires physical integrity as well as high electrical conductivity. The conventional bonding processes used to bond an external wire of the package to the bond pad of the integrated circuit, typically require either elevated temperatures, high pressures, or both, as well as ultrasonic energy. These effects are required to produce a connection between the bond pad and the external wire which is of high physical integrity and low electrical resistance. These conditions used for coupling the wire to the bond pad, however, can cause defects in a dielectric film over which the bond pad is typically formed.
Bond pads are conventionally formed over dielectric materials to electrically insulate the bond pad metal from the substrate and from other electrical devices which may be formed beneath the bond pads. The conditions of conventional methods used to couple external wires to bond pads, can produce mechanical stresses in the dielectric film formed beneath the bond pad. The stresses may cause defects which can result in leakage currents through the dielectric formed between the bond pads and the underlying substrate, which is frequently electrically conducting, and other devices if they are formed beneath the bond pads. As such, using conventional processing technology, these leakage currents preclude incorporating active devices beneath the bond pads. This limitation decreases the level of integration and the efficient use of substrate space for device purposes.
Attempts have been made to use the substrate area underneath the bond pads for active device purposes. Attempts have been made using conventional wire bonding technology. For example, U.S. Pat. No. 5,751,065 to Chittipeddi, et al. discloses providing an additional layer of metal beneath the dielectric formed beneath the bond pad, in order to minimize the effect of the stress of the bonding process, upon the substrate and the other devices formed beneath the bond pad. Metal is malleable and acts to absorb the stress. This technique using the additional metal layer, however, requires an additional sequence of process steps directed to depositing and patterning the metal film in order to produce the modified bond pad structure. These additional processing steps take time and add production and material costs to the production of an integrated circuit.
The present invention addresses the shortcomings of previous techniques, and provides a novel process for forming a bond pad structure which allows for the area beneath the bond pads to be utilized for active devices. The process does not require the formation of a separate metal film directed to accommodating the stresses produced using conventional wire bonding techniques.
The process of the present invention includes forming a dual damascene bond pad over active circuitry within an integrated circuit device. The process includes the steps of forming a bond pad opening, depositing a barrier layer film to form the bottom surface of an upper section of the bond pad opening, and forming vias which extend vertically through the bottom of the bond pad opening to form a dual damascene structure. The bond pad opening is then filled with a metal material. The vias may provide for connection between the bond pad metal and active circuitry formed beneath the bond pad. The bond pad formed according to the process of the present invention is resistant to stress effects such as leakage which may occur during wire bonding of the bond pad to an external wire.